Alif Semiconductor /AE512F80F55D5AS_CM55_HE_View /CLKCTL_PER_SLV /UART_CTRL

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as UART_CTRL

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (Val_0x0)CKEN0 (Val_0x0)CLK_SEL0 (Val_0x0)RS4850 (Val_0x0)DMA_SEL

RS485=Val_0x0, CLK_SEL=Val_0x0, DMA_SEL=Val_0x0, CKEN=Val_0x0

Description

UART Control Register

Fields

CKEN

UART[7-0] Enable. One bit for each module. Bit 7 --> UART7, bit 0 --> UART0

0 (Val_0x0): Disable UART[7-0] module

1 (Val_0x1): Enable UART[7-0] module

CLK_SEL

UART[7-0]_SCLK Select. One bit for each module. Bit 15 --> UART7, bit 8 --> UART0.

0 (Val_0x0): 38.4 MHz

1 (Val_0x1): SYST_PCLK clock

RS485

UART[7-4] RS485 Status. One bit for each module. Bit 23 --> UART7, bit 20 --> UART4. Bits[19-16] are reserved.

0 (Val_0x0): UART not in RS485 mode

1 (Val_0x1): UART is in RS485 mode

DMA_SEL

UART DMA select for UART[7-4]. One bit for each module. Bit 27 --> UART7, bit 24 --> UART4.

0 (Val_0x0): Select DMA0

1 (Val_0x1): Select DMA1

Links

() ()